This invention relates to the key circuits used in small electronic calculators with key switches, and more particularly to key circuits contained in low power consumption integrated circuits or integrated circuits in which key switch on-resistance or load capacity may present a problem.
With the development of large scale integrated circuits, integrated circuits with CMOS (complementary metal oxide semiconductor) structure, particularly the clock synchronized type, C.sup.2 (clock synchronized complementary) MOS structure, have been employed for electronic calculators or electronic clocks. With the use of these MOS structure integrated circuits, regardless of whether the circuits perform calculation or display functions, the power consumption can be limited to only several microamperes. Since the power consumption is small, solar cells can be used as a means of power supply. In this type of integrated circuits, the read-in of key signals is performed by using the difference of on-resistance between P-channel and N-channel MOS transistors. Accordingly, if the factors, such as duty of the pulse signal for controlling the ON/OFF operation of these transistors or on-resistances of these transistors, is not considered, a large current (through-current) will flow through these transistors over a significantly long period of time.
FIG. 1 shows an example of a conventional key circuit.
FIGS. 2A to FIG. 2P illustrate timings of signals at various portions in the key circuit when key switch 36.sub.6 provided between external terminals 32 and 34 is closed. FIG. 2A represents reference pulse signal P, FIG. 2B is sinchronizing signal .phi.A, FIGS. 2C and 2D are the output signals Q1 and Q2 of binary counters 11 and 12, FIGS. 2E to 2H are time-division signals D1 to D4, which are output from decoder 13, FIGS. 2I to 2L are external signals VK1 to VK4, which are input to external terminals 31 to 34, respectively. FIGS. 2M to 2P are key signals KA to KD, which are output from latch circuits 53 to 56.
In the key circuit of FIG. 1, two binary counters 11 and 12 are connected in series. Counter 11 is input with a fixed period reference pulse signal P (FIG. 2A), and counts it. When counter 11 has counted a predetermined number of pulse signals P, it outputs pulse signal Q1 (FIG. 2C). Output pulse signal Q1 is then input to counter 12, and counted. When counter 12 has counted a predetermined number of pulse signals Q1, it output pulse signal Q2. (FIG. 2D). The output pulses Q1 and Q2 of counters 11 and 12 are input to decoder 13. Decoder 13 generates and outputs time-division signals D1 to D4, (FIGS. 2E to 2H) based on pulse signals Q1 and Q2. Time-division signals D1 to D4 are then inverted by inverters 14 to 17, respectively, and input to buffer circuits 26 to 29. Buffer circuit 26 is composed of P-channel MOS transistor 18 and N-channel MOS transistor 22, which are connected in series between power supply potential V.sub.DD and reference potential V.sub.SS. The gates of transistors 18 and 22 are connected. Buffer circuit 27 is composed of P-channel MOS transistor 19 and N-channel MOS transistor 23, which are also connected in series between power supply potential V.sub.DD and reference potential V.sub.SS. The gates of transistors 19 and 23 are connected. Buffer circuit 28 is composed of P-channel MOS transistor 20 and N-channel MOS transistor 24, which are connected in series between power supply potential V.sub.DD and reference potential V.sub.SS. The gates of transistors 20 and 24 are connected. Buffer circuit 29 is composed of P-channel MOS transistor 21 and N-channel MOS transistor 25, which are connected in series between power supply potential V.sub.DD and reference potential V.sub.SS. The gates of transistors 21 and 25 are connected.
The output signals of buffer circuits 26 to 29 are supplied to external terminals 31 to 34, respectively. Terminal 31 is used exclusively for output, and terminals 32 to 34 both for input and output. External terminal 35 is used for input purposes. Touch-switch type key switches 36.sub.1 to 36.sub.10 are used between each of pair of the adjacent terminals 31 to 35. The output signals of inverters 15 to 17, which are inversions of time-division signals D2, D3 and D4, are input to AND gate 37. The signal from external terminal 32 is also input to AND gate 37. The output signals of inverters 16 and 17, which are inversions of time-division signals D3 and D4, and also the signal from external terminal 33 are input to AND gate 38. The output signal of inverter 17, which is the inversion of time-division signal D4, and also the signal from external terminal 34 are input to AND gate 39. N-channel MOS transistor 40, which is always in the ON state and whose gate is connected to power supply potential V.sub.DD, is connected between external terminal 35 and the reference potential V.sub.SS. The output signals of AND gates 37 to 39 are input and latched into latch circuits 53 to 55, respectively. The signals of AND gates 37 to 39 are synchronized with synchronizing signal .phi.A (FIG. 2B), and output as key signals KA to KC (FIGS. 2M to 20). The signal from external terminal 35 is input and latched into latch circuit 56, where it is synchronized with synchronizing signal .phi.A, and output as key signal KD (FIG. 2P).
Latch circuit 53 is composed of clocked inverter 41, which receives the output signal from AND gate 37, and operates in synchronism with synchronizing signal .phi.A; inverter 45, which inverts the output of clocked inverter 41; and clocked inverter 49, which is connected in inverse parallel with inverter 45, and operates in synchronism with the inverted signal of synchronizing signal .phi.A. Latch circuit 54 is composed of clocked inverter 42, which receives the output signal from AND gate 38, and operates in synchronism with synchronizing signal .phi.A; inverter 46, which inverts the output of clocked inverter 42; and clocked inverter 50, which is connected in inverse parallel with inverter 46, and operates in synchronism with the inverted signal of synchronizing signal .phi.A. Latch circuit 55 is composed of clocked inverter 43, which receives the output signal from AND gate 39, and operates in synchronism with synchronizing signal .phi.A; inverter 47, which inverts the output of clocked inverter 43; and clocked inverter 51, which is connected in inverse parallel with inverter 47, and operates in synchronism with the inverted signal of synchronizing signal .phi.A. Latch circuit 56 is composed of clocked inverter 44, which receives the output signal from external terminal 35 and operates in synchronism with synchronizing signal .phi.A; inverter 48, which inverts the output of clocked inverter 44; and clocked inverter 52, which is connected in inverse parallel with inverter 48, and operates in synchronism with synchronizing signal .phi.A.
Parasitic capacitance is present between external terminals 31 to 35, and between each external terminal and power supply potential V.sub.DD or reference potential V.sub.SS. In order to simplify the drawing, only the capacitance parasitic on external terminal 32, capacitances 57 to 61 are shown in FIG. 1.
In the key circuit configured as explained above, time-division signals D1 to D4 are generated in decoder 13, phase-inverted by inverters 14 to 17, and input to AND gates 37 to 39 respectively. The signals D2 to D4, and the signals output from external terminals 32 to 34 are then ANDed by AND gates 37 to 39. These AND signals are then input to the latch circuits, and key signals KA to KD, which correspond to the selective closing of key switches 36.sub.1 to 36.sub.10, are obtained. In order to detect key signals KA to KD, the dimensions of P-channel MOS transistors 18 to 21 with on-resistance of Rp and N-channel MOS transistors 22 to 25 and 40 with on-resistance of Rn, are set so that Rp is smaller than Rn (Rp&lt;Rn).
In the key switch circuit of FIG. 1, when a key switch, for example, key switch 36.sub.6, is closed, after the time-division signal D2 is output from decoder 13, key signals KA to KD will be logic levels "0", "0", "1" and "0", respectively. With detection of these key signals KA to KD, it can be understood that key switch 36.sub.6 is closed.
FIG. 3 is an equivalent circuit of the circuit shown in FIG. 1, when key switch 36.sub.6 is closed.
As shown in FIG. 3, the equivalent circuit is composed of inverters 15 and 17, buffer circuits 27 and 29, external terminals 32 and 34, AND gates 37 and 39, and on-resistance Rkey of key switch 36.sub.6, which is connected between external terminals 32 and 34. Capacitor C represents the external load capacitance of external terminals 32 and 34, or parasitic capacitance.
FIGS. 4A to 4E show the timing charts at various portions in the equivalent circuit of FIG. 3. In the equivalent circuit of FIG. 3, during the period that time-division signal D2 is at "1" level, the P-channel MOS transistor 19 in buffer circuit 27 is turned on. At this time, the time-division signal D4 is at "0" level and N-channel MOS transistor 25 in buffer circuit 29 is also turned on. Accordingly, at this time, the potential VK2 is determined by the voltage division of the on-resistance Rp of the P-channel MOS transistor 19 in buffer circuit 27, the on-resistance Rkey of key switch 36.sub.6, and the on-resistance Rn of N-channel MOS transistor 25 in buffer circuit 29. At this time, a through-current flows between power supply potential V.sub.DD and reference potential V.sub.SS. On the other hand, during the period that time-division signal D4 is "1" level, P-channel MOS transistor 21 in buffer circuit 29 is in the ON state. Time-division signal D2 is at "0" level, and N-channel MOS transistor 23 in buffer circuit 29 is ON. The potential VK4 at external terminal 34 is determined by the voltage division produced by the on-resistance Rp of P-channel MOS transistor 21 in buffer circuit 29, the on-resistance Rkey of key switch 36.sub.6, and the on-resistance Rn of N-channel MOS transistor 23 in buffer circuit 27. At this time, a current flows between power supply potential V.sub.DD and reference potential V.sub.SS. In this circuit, during the period T1 that signals D2 and D4 are at "1" level, as shown by T1 of FIGS. 4A to 4E, a through-current will flow.
The through-current, Ishort is given by ##EQU1## where, Rp+Rkey&lt;Rn. As may be seen from the equation (1), through-current Ishort depends on the on-resistance Rn of N-channel MOS transistors 23 and 25 in buffer circuits 27 and 29. The larger these values is, the lower the through-current value is.
Also, during the period that signal D2 is at "1" level, the potential VK2 of external terminal 32, which receives its input from AND gate 37, can be expressed EQU VK2=Rn.multidot.V.sub.DD /(Rp+Rkey+Rn) 2
As seen from the above equation (2), potential VK2 of external terminal 32 increases as the on-resistance value Rn of N-channel MOS transistor 25 in buffer circuit 29 increases, and the input margin is thereby improved. This relationship also applies to the potential VK4 at external terminal 34. When signal D4 is at "1" level, the value of potential VK4 of external terminal 34, which receives its input from AND gate 39, is EQU VK4=Rn.multidot.V.sub.DD /(Rp+Rkey+Rn) 3
During the period T1, when the through-current is flowing, the external load capacitors C are charged by potential V.sub.DD ; then, if D2 or D4 is changed to "0" level (represented by period T2), then these capacitor C will be discharged by N-channel MOS transistors 23 and 25 in buffer circuits 27 and 29. Then, the potential VK2 at external terminal 32, which varies in accordance with the transient phenomenal characteristics at the time of this discharge, is expressed ##EQU2## This may correspondingly be applied for the potential VK4 at terminal 34, and is given. ##EQU3##
During the period of time T2 from the discharge start time t0 to the time t1 at which the synchronizing signal .phi.A drops, if e(t) does not drop to such a potential that AND gate 37 or 39 detects that the level of e(t) is "0" level, an error operation will occur.
Recent technology in this field improves the checking ability by the key to shorten the detection time period. Further, use of large key switches or film keys increases the load capacitance C. Allowing for these facts, the smaller the on-resistance value of Rn of N-channel MOS transistors 22 to 25 in buffer circuit 26 to 29, the better the input margin response during time period T2.
In the past, the appropriate setting of the on-resistance of N-channel MOS transistors in the buffer circuit has been used to solve the two reciprocal problems concerning through-current and key input margin. Therefore, undesirable limitations must be imposed on the process parameters in manufacturing N-channel MOS transistors in integrated circuits. Further, the key switch 36 used must have small on-resistance and capacitance. This leads to increase of production cost.